VLSI Constraints Classification

Constraints Handling - A very broad classification of constraints

1. Clock Constraints
2. IO Constraints
3. Exceptions and case analysis
4. Operating conditions and OCV

A very widely used format called as SDC (Synopsys Design Constraints) is used to describe the constraints. For each constraint type, corresponding SDC command is given in in blue color. 

1. Clock Constraints

• Multiple clock definitions create_clock
  
• Clock network delay and Skew set_propogated_clock and set_clock_latency, set_clock_uncertainty
• Generated clocks create_generated_clock
• Clock Transition time set_clock_transition
• Gated clocks set_clock_gating_check

2. IO Constraints

• Input and output delays set_input_delay and set_output_delay
• Driving cell and input transition set_driving_cell and set_input_transition
• Output capacitance set_load

3. Exceptions and case analysis

• Multicycle paths set_multicycle_path
• False path set_false_path
• Disable Timing set_disable_timing
• Case Analysis set_case_analysis

4. Operating Conditions and Derates

• Single,bc_wc,ocv - set_operating_conditions
  
• Applying derates – set_timing_derate
• CRPR – timing_remove_clock_reconvergence_pessimism

Note: Very few important constraints are discussed here. There are plenty of other commands in SDC.